## 2022写essay的技巧新的OLED像素电路及其抑制电压漂移的a

新的OLED像素电路及其抑制电压漂移的a-Si：H TFT的驱动方法-留学生论文46.2: New OLED Pixel Circuit and Driving Method to Suppress ThresholdVoltage Shift of a-Si:H TFTTaro Hasumi, Shinji Takasugi, Keigo Kanoh, Yoshinao KobayashiR&D Center, Kyocera Display Institute Co., Ltd., Yamato-Shi, Kanagawa, Japan摘要 Abstract提出一种新的有机发光二极管（OLED）的像素以此来补偿电路，可变电容器阈值电压（Vth）完全转移，同时也提出了一个像素驱动的方法来抑制Vth偏移。We propose a new organic light-emitting diode (OLED) pixelcircuit with a variable capacitor that allows to compensatethreshold voltage (Vth) shift completely, and also propose a pixeldriving method to suppress Vth shift. http://www.ukassignment.org/dxessay/简介 1. IntroductionAmorphous silicon (a-Si) TFT arrays are widely used in the LCDindustry and they are one of the most cost-effective candidates foractive-matrix organic light-emitting diode displays (AMOLEDs)[1] [2]. However, a-Si TFTs have been considered to have asevere Vth shift caused by long-time operations, which results inluminance deterioration and image sticking of display devices.目标是抑制Vth偏移，并补偿Vth偏移，并且使用的a-Si TFT作为AMOLED显示器的可靠底板。Our objective is to suppress Vth shift and to compensate Vth shiftcompletely if any, and to use a-Si TFTs as a reliable backplane forAMOLEDs.放电模式的a-Si：H TFT驱动 2. Discharging Mode for a-Si:H TFT DrivingVth shift of a-Si TFTs due to consecutive gate biases has beenregarded as the most difficult issue for the use of a-Si TFTs as anAMOLED backplane. Two possible mechanisms of theinstability of a-Si TFTs have been investigated; one is creation ofmetastable states on a-Si:H and the other is charge trapping in thesilicon nitride gate insulator [3]. Although it is not clear yetwhich of the two mechanisms dominates the instability, someexperimental results indicate that applying a negative biassuppresses Vth shift, which occurs during positive bias periods[4]. We investigated negative bias conditions in detail on biasand time dependencies of suppression of Vth shift.We measured Vth shift of driving TFTs with the following“Constant Current BTS” method: a driving TFT is controlled tohave a constant drain current (Ids) by automatically adjusting itsgate bias (Vgs), while its drain bias (Vds) is fixed to a constantvoltage. Assuming that mobility degradation is negligible, wetreat gate bias shift (Vgs – Vth) is equal to Vth shift. Under ourtesting condition (mobility = 0.5cm/Vs2, Cox = 17nF/cm2, Ids =0.4μA, Vds = 6V), mobility degradation did not occur. We cantherefore regard V0 (Vgs – Vth) shift as the Vth shift of thedriving TFT. A gate bias was automatically applied for the TFTto have an Ids of 0.4μA (V0 is a positive value around 3V). Wealso raised the environment temperature to 40°C, emulatingOLED heat. At certain predetermined intervals, which we calldischarging mode, the gate bias was set to negative.Some of our results are shown in Figs. 1-3 (points are actual driftsof V0, and lines are approximation lines), in which tests weapplied negative biases -1V or -5V for 20min, after applying apositive bias for 10min. It is clear from the slopes of V0 shiftthat negative biases suppress Vth shift. The TFT of a bias of -5Vhas a Vth shift of nearly 0, which indicates we can suppress Vthshift of a-Si TFTs significantly by selecting an appropriatenegative bias.No Discharing0.010.11100.01 1 100 10000Stressed time[H]ΔＶ0after 10000hVth shift = 2.7VFigure 1:Vth Shift of BTS Test without DischargingDischarging -1V0.010.11100.01 1 100 10000Stressed time[H]ΔＶ0after 10000hVth shift = 1.2VFigure 2:Vth shift of BTS Test with –1V dischargingDischarging -5V0.010.11100.01 1 100 10000Stressed time[H]ΔＶafter 10000hVth shift = 0.08VFigure 3 Vth shift of BTS Test with –5V dischargingWe have also checked shorter periods and found out even 15s and60s of a negative bias (Vgs = -5V, Vds = 0V) also suppressed Vthshift significantly. Figs. 4 and 5 are the BTS results of 15s and60s of a negative bias of -5V. The stress condition was the sameas that of Figs. 1-3. The result of -5V for 15s is better than that ofFig. 1, and we see from these results that we can easily use46.2 / T. Hasumidischarging mode to suppress Vth shift for actual displayapplications such as when a display is turned off for batterysaving.Discharging -5V for 15seconds.0.010.11100.01 1 100 10000Stressed time[H]ΔＶ0after 10000hVth shift = 0.51VFigure 4 Vth shift of BTS Test with –5V 15s dischargingDischarging -5V for 60seconds.0.010.11100.01 1 100 10000Stressed time[H]ΔＶ0after 10000hVth shift = 0.34VFigure 5 Vth shift of BTS Test with –5V 60s dischargingOur design assumption for AMOLED TFTs is that the maximumIds for a driving TFT is 0.1μA through 5μA, and we use drivingTFTs only in their saturation region even at the maximum pixelluminance. We calculated that the gate bias (Vgs – Vth) ofdriving TFTs will be lower than 5V. At these stress conditions,Vth shift of stressed TFTs recovers at 230°C annealing, whilemobility degradation does not occur.0.E+002.E-054.E-056.E-058.E-051.E-040 5 10 15 20Vgs[V]Ids[A]Before StressAfter StressStress+AnnealVth Shiftby StressRecover byAnnealFigure 6 Before Stress/After Stress/Stress+Anneal IV CurveFig. 6 shows the initial, stressed (caused a Vth shift of 8V), andafter-annealing Id-Vg curves. We can see that the TFTrecovered from Vth shift completely, which result suggests Vthshift of a-Si TFTs is due to a metastable change of a-Si:H, and thechange can be cured through negative biases or annealing.3. Complete Vth Compensation新型TFT像素电路 3.1 Novel 2-TFT Pixel CircuitFig. 7 shows our novel 2-TFT pixel circuit of complete Vthcompensation.COLEDTdVSS lineData lineCgsTth OLEDCgsTdCgdTdScan lineCgdTthVDD lineCsCvar TthFigure 7 Novel 2-TFT pixel circuit每个像素电路的驱动用TFT（Td）的一个Vth的检测TFT（Tth），存储电容（Cs），可变电容器（CVAR），和一个OLED，并连接到对应的扫描线及数据线VDD线的和VSS线。Each pixel circuit has a driving TFT (Td), a Vth sense TFT (Tth),a storage capacitor (Cs), a variable capacitor (Cvar), and anOLED, and is connected to corresponding scan line and data line,and to the common VDD line and VSS line. The OLEDcapacitance (COLED) and unintentional parasitic capacitances ofTFTs (CgdTd, CgsTd, CgdTth, CgsTth) are also shown. Wehave found that because of the parasitic capacitances, we usuallycannot compensate Vth just by Vth sense. We introduce thevariable capacitor to compensate Vth completely.3.2 Driving SchemeFig. 8 shows the driving waveforms of the 2-TFT pixel circuits.VDD lineVSS linePreparationVth senseWriting Emission-Vp0VDDVDD0Scan line 1 VgHVgLData line VdH0Reset Cs Reset OLED-VpVgHVgL Scan line 2scan::Figure 8 Pixel driving waveformsPixel rows are scanned vertically during the writing period, whileother periods including the emission period are simultaneous.46.2 / T. HasumiWhen the Vth sense period ends, Cs and COLED of each pixel holda voltage of Vth + a, where Vth is the threshold voltage of the Tdof the pixel and a is a constant depending on the duration of theVth sense period and the capacitance ratio of the pixel.3.3 Voltage CalculationBefore calculating a pixel voltage, we define the following twocapacitances:Call = COLED + Cs + CgsTthon + CgdTthon + CgsTdoff + Cvaron#p#分页标题#e#Call’ = Cs + CgsTthoff + CgsTdon + CgdTdoff + CvaroffThe parasitic capacitances have different capacitance values whenthe corresponding TFT is on and off, and we use suffixes todistinguish them here. Likewise, the variable capacitor has twocapacitance values. We also define three capacitance differenceshere:ΔCgsTd = CgsTdon – CgsTdoffΔCgsTth = CgsTthon – CgsTthoffΔCvar = Cvaron – CvaroffWhen the image data voltage Vdata is written to a pixel, the Tdgate voltage Vgswrite is calculated as follows:Vgswrite = Vth + a + (Cs / Call) VdataThe Td gate voltage Vgs during the emission period is calculatedas follows:Vgs = {(Cs + CgsTthon + CgsTdoff + Cvaron) / Call’} (Vth + a) +{Cs (COLED + CgdTthon) / (Call Call’)} Vdata + {-(CgsTthon +Cvaron) VgH + (CgsTthoff + Cvaroff) VgL + CgdTdoff Vds} / Call’The value of ∂(Vgs – Vth)/∂Vth must be 0 in order to compensateVth completely.∂(Vgs – Vth)/∂Vth = (-CgsTdon – ΔCgsTd + ΔCgsTth + ΔCvar) =0∴ ΔCvar = CgsTdon + ΔCgsTd – ΔCgsTthIn this case Vgs can be simplified to:Vgs = Vth + b Vdata + cwhere b and c are constant. Since Ids is given in the followingequation, we obtain the same Ids for the same Vdata:Ids = (β / 2) (Vgs – Vth)2 = (β / 2) (b Vdata + c)2Since Td is larger than Tth, (CgsTdon + ΔCgsTd) is larger thanΔCgsTth. We need a variable capacitor large enough tocompensate Vth.3.4 Slit MIS Capacitor为了在有限的空间中形成的可变电容器像素，我们引入一个金属 – 绝缘体 – 半导体（MIS）电容，一个新的可变电容器组成的平常源极/漏极层和a-Si层。 In order to form a variable capacitor in the limited space of apixel, we introduce a slit metal-insulator-semiconductor (MIS)capacitor, a novel variable capacitor consisting of usual gate andsource/drain layers and an a-Si layer. Fig. 10 shows the conceptof the slit MIS capacitor. M1 is the gate layer and M2 is thesource/drain layer, although a slit capacitor does not function as atransistor. When the M1 voltage is low, a-Si becomes aninsulator and the M1/M2 overlapping area works as a capacitor.When the M1 voltage is high, a-Si becomes a conductor and theM1/a-Si overlapping area works as a capacitor. We put a slitMIS capacitor in a pixel to compensate the parasitic capacitances,and we can completely compensate Vth shift if any.M1a-SiM2Figure 10 The concept of the slit MIS capacitorFig. 11 shows actual data of capacitance per area of a plain metalinsulator-metal (MIM) capacitor, a plain MIS capacitor, and a slitMIS capacitor of a line width of 3μm and a slit width of 6μm.Fig. 12 shows the relationship of the slit width and capacitanceper area when the line width is fixed to 3μm.020406080100120140160180200-20 -15 -10 -5 0 5 10 15 20Bias [V]Capacitance per area [μF/m2]M1/M2M1/a-Si/M2M1/a-Si/M2 slit3/6Figure 11 Bias vs. capacitance per area0501001502000 10 20 30 40Slit width (μm)Capacitance per area (μF/m2)Bias = -20VBias = +20VFigure 12 Slit width vs. capacitance per area3.5 Effect of Complete Vth CompensationBy properly designing the size of the variable capacitor, we havesuccessfully compensated Vth completely. Actual luminance46.2 / T. Hasumidata with and without complete Vth compensation tests are shownin Figs. 13 and 14.024681012140 32 64 96 128 160 192 224 256LevelLuminance1/2 (cd1/2/m)0h100h300h500hFigure 13 Luminance (Complete Vth Compensation)024681012140 32 64 96 128 160 192 224 256LevelLuminance1/2 (cd1/2/m)0h100h300h500hFigure 14 Luminance (Incomplete Vth Compensation)4. Fabrication of a-Si:H Driven AMOLEDsUsing the above-mentioned 2-TFT pixel with complete Vthcompensation, we have successfully fabricated 2.4” qVGA a-Si:Hdriven AMOLEDs.The specification of the AMOLEDs is described in Table 1, and aphotograph of one of them is shown in Fig. 15.Size 2.4"Format qVGA (320 x 240)Resolution 166ppiContrast Ratio 2000:1>Peek Brightness 200cd/m2Color Saturation (NTSC) 90%Table 1 The specification of the actual AMOLEDFigure 15 A photograph of one of our AMOLEDs结论 5. Conclusion结合的放电模式和完整的Vth补充我们已经成功地抑制了的a-Si TFT的阈值电压偏移，这样我们从而提出a-Si TFT可以作为一个在技术上和经济上可行的AMOLED背板。Combining the discharging mode and complete Vth compensationwe have successfully suppressed Vth shift of a-Si TFTs, and wethus propose a-Si TFTs as a technologically and economicallyviable AMOLED backplane.6. AcknowledgementsWe would like to thank Kazuo Inamori and Yasuo Nishiguchi forsupporting this research and development operation. We alsothank Hidenori Miyata and Mototsugu Ohhata for their leadership.We give thanks to all the colleagues in Kyocera Display Institutefor effective suggestions and cooperation.7. References[1] T. Tsujimura et al., “A 20-inch OLED Display Driven bySuper-Amorphous-Silicon Technology”,SID 03 Digest, pp6-9, 2003.[2] S. Ono et al., “Pixel Circuit for a-Si AM-OLED”,IDW '03 Digest, pp255-258, 2003.[3] M. J. Powell, “Bias-stress-induced creation and removal ofdangling-bond states in amorphous silicon thin-filmtransistors”, Appl. Phys. Lett. Vol 60, pp207-209, 1992.[4] J. H. Lee et al., “A New a-Si:H TFT Pixel CircuitSuppressing OLED Current Error Caused by the Hysteresisand Threshold Voltage Shift for Active Matrix Organic LightEmitting Diode”, SID 05 Digest, pp228-231, 2005.