Page 1 of 5 UNIVERSITY OF BRISTOL JANUARY 2018 FACULTY OF ENGINEERING Examination for the Degrees of Bachelor and Master of Engineering EENG26000 Electronics 2 TIME ALLOWED: 2 Hours This paper contains three questions. Each question carries 20 marks. The paper carries a total of 60 marks. Attempt all questions. The maximum for this paper is 60 marks. Other Instructions 1. Calculators must have the Engineering Faculty seal of approval. TURN OVER ONLY WHEN TOLD TO START WRITING Page 2 of 5 Q1 (a) Compare and contrast the different types of BJT amplifier available to an electronics design engineer. You should include discussion of input resistance, output resistance, voltage gain and current gain for each type of amplifier. Also state whether the configuration is unilateral. Answering in the form of a table is acceptable. (7 marks) (b) Figure Q1 shows a particular amplifier configuration (i) Which configuration is shown? (2 marks) (ii) Sketch the small signal equivalent T-model for this amplifier (4 marks) (iii) Derive expressions for the input and output resistances of the amplifier (3 marks) (iv) Derive expressions for the voltage gain (vo/vs) and current gain (io/ii) of the amplifier (4 marks) Figure Q1 ii io Page 3 of 5 Q2 (a) Draw a diagram showing the basic structure of a n-channel Enhancement mode MOSFET when both Source and Drain are connected to ground and a positive voltage is applied to the Gate. Label all features in the diagram. (2 marks) (b) Draw a diagram of the same structure as in part (a) above but now with a positive Drain-Source voltage applied and explain how this enables the device to operate as an amplifier. (4 marks) (c) Sketch the output Current-Voltage curves for a MOSFET as described in part (b). Highlight any important features and regions of operation for the device (3 marks) (d) In the circuit of figure Q2, the MOSFET may be considered to be biased into the saturation region such that ID = 10mA with a value of gm = 2.5mA/V. The drain resistance, RD = 60k. At the operating frequency, the device capacitances are sufficiently small and the circuit capacitances sufficiently large to be neglected. (i) Draw the small signal model for the circuit (4 marks) (ii) Calculate the small-signal voltage gain when the load resistance, RL = 70k. (Assume that VA = 100V) (3 marks) (e) Explain what limits the upper frequency of operation of a silicon MOSFET and suggest two changes to the device that could increase the upper frequency limit (4 marks) Page 4 of 5 DDV 1GR 2GR DR SR LR Figure Q2 Page 5 of 5 Q3 (a) (i) Discuss with the aid of diagrams the operation of the Wien Bridge oscillator. (5 marks) (ii) Explain what controls the final amplitude of an oscillator and show with the aid of diagrams how the amplitude of the Wein Bridge oscillator in (i) can be controlled. (5 marks) (b) Figure Q3 shows a simplified diagram of a Hartley oscillator. (i) Sketch the small signal equivalent circuit for this oscillator (7 marks) (ii) It is desired to operate the oscillator at 1MHz, if the transistor is biased such that the value of gm = 30mA/V, calculate the required values of L1 and L2. (3 marks) Figure Q3
